High speed serial (HSS) links have, in many cases, replaced shared parallel buses in such areas as storage devices, multimedia PCs, entertainment systems, and telecom systems. As a result, standard interfaces such as XAUI (Xilinx Attachment Unit Interface), Serial ATA (Advanced Technology Attachment), PCI (Peripheral Component Interconnect) Express, HDMI (High Definition Multimedia Interface), and FB-DIMM (Fully Buffered Dual In-Line Memory Module) have emerged to provide improved throughput using serial signaling rates in the GHz range.
HSS links provide distinct system implementation advantages. When compared to traditional parallel interfaces, HSS links can provide lower cost by using fewer I/O pins and simplified routing. Printed circuit board (PCB) area used for connecting signals can be reduced substantially because of the utilization of fewer layers, fewer components, and the reduction of on-board termination elements. Because differential signals are commonly used with HSS links, noise tolerance is improved, better voltage margins are achieved, and electromagnetic interference (EMI) radiation is reduced. HSS links can also reduce data skew among multiple parallel lines. In addition, since the clock may be embedded in the serial data stream, issues of timing and clock skew may be reduced as well.
While the advantages of HSS links have driven the standardization and fast adoption of HSS links, HSS links present many challenges to designers. Reliable signal transmission across a motherboard or between daughter cards may be difficult to achieve at GHz speeds. As data rates approach 3 Gbit/s and higher, the number of variables for which a board designer must account is enormously complex. A quantitative understanding of such variables as dielectric constant, return loss, inter-symbol interference (ISI) jitter, and dynamic variances such as temperature and humidity change is necessary to achieve GHz speeds.
HSS links often have a maximum limit for BER (bit error rate). BER is the percentage of bits with errors divided by the total number of bits that have been transmitted, received or processed over a given time period. JEDEC (Joint Electronic Devices Engineering Council, part of the Electronic Industries Association that publishes specifications and standards for electronic components) specifies in its FBD (Fully Buffered DIMM) specification, for example, a maximum BER of 10−12 bits/sec when driving from a memory controller to a DIMM (dual in-line memory module). When a HSS link becomes physically too long, the BER on that link may increase beyond the required specification. In this type of situation, it becomes necessary to reduce the BER without sacrificing frequency requirements or changing the electrical characteristics of the board.
There is a need in the art for an electronic device that improves BER on HSS links that would otherwise fail to meet a required specification.